In recent years, various types of digital wired communication devices have required capability to transmit a large amount of data, with an increase in the number of users or the spreading of multimedia communication. A bit error rate which is defined as the comparison between the number of data items in which a code error occurs among the received data items and the total number of received data items has been known as one of the indexes for evaluating the quality of a digital signal in the digital wired communication device.
For example, the following Patent Document 1 discloses an error rate measurement device as a measurement device for measuring the bit error rate.
The error rate measurement device transmits a test signal including fixed data to the object to be measured, which is a device under test that includes various electronic components, such as an optical converter, compares a reference signal and the signal to be amplified, which is transmitted from the object to be measured in response to the input of the test signal, bit by bit, and measures the error rate of the signal to be amplified. FIG. 6 is a diagram illustrating the schematic structure of the error rate measurement device disclosed in the following Patent Document 1.
An error rate measurement device 101 shown in FIG. 6 includes a data storage unit 101a which is formed by a memory, such as a RAM, a comparative data storage unit 101b, a positional information storage unit 101c, a signal transmitting unit 101d which is formed by, for example, an integrated circuit, a signal receiving unit 101e, a synchronous detection unit 101f, a comparison unit 101g, a display control unit 101h, a display device 101i, such as a CRT display or a liquid crystal display, and an operation unit 101j such as a keyboard. The error rate measurement device 101 compares input data which is received from an object 102 to be measured with the known data to be received from the object 102 to be measured, sequentially stores bit strings of comparative data including one bit or a plurality of bits which are detected under a predetermined detection condition in a plurality of blocks in order of detection, and displays each bit string which is obtained from the comparative data stored in each of the plurality of blocks on the display device 101i so as to be arranged on the basis of the position satisfying a predetermined arrangement condition.
However, when the error rate measurement device 101 measures the error rate of a non-return-to-zero (NRZ) signal used in data communication as the signal to be amplified, an NRZ signal amplifying device which amplifies the NRZ signal to a desired level is used.
FIG. 7 is a block diagram illustrating the structure of the NRZ signal amplifying device disclosed in the following Patent Document 2. An NRZ signal amplifying device 201 shown in FIG. 7 has an automatic adjustment function which constantly operates a loop for detecting the center voltage of an input voltage to a main amplifier 203 and for setting an offset voltage applied to an offset circuit 202 to constantly automatically adjust the offset voltage suitable for the center voltage of the input voltage.
Furthermore, the NRZ signal amplifying device 201 includes: an offset circuit 202 that applies the offset voltage to an NRZ signal which is input as the signal to be amplified and outputs the signal; a main amplifier 203 that receives an output signal from the offset circuit 202 and amplifies the output signal; voltage detection means 204 for detecting a high-level voltage and a low-level voltage of an input signal to the main amplifier 203; A/D converters 205 (205a and 205b) that convert the high-level voltage and the low-level voltage detected by the voltage detection means 204 into digital values; center voltage calculation means 206 for calculating a center voltage between the high-level voltage and the low-level voltage on the basis of the digital values converted by the A/D converters 205; and offset voltage setting means 207 for calculating an offset voltage at which the center voltage calculated by the center voltage calculation means 206 is substantially the center of the appropriate input range of the main amplifier 203 and gives the offset voltage to the offset circuit 202.
The voltage detection means 204 includes: a first comparator 204a that compares an input signal Sa to the main amplifier 203 with a first reference voltage Vs1; a second comparator 204b that compares the input signal Sa to the main amplifier 203 with a second reference voltage Vs2; a first filter 204c that extracts a DC component from an output signal C1 from the first comparator 204a; a second filter 204d that extracts a DC component from an output signal C2 from the second comparator 204b; a first operational amplifier 204e that receives an output signal DC1 from the first filter 204c and a first standard voltage Vr1 equal to an output upper limit voltage from the first comparator 204a and gives a difference output therebetween as a first reference voltage Vs1 to the first comparator 204a; and a second operational amplifier 204f that receives an output signal DC2 from the second filter 204d and a second standard voltage Vr2 equal to an output upper limit voltage from the second comparator 204b and gives a difference output therebetween as a second reference voltage Vs2 to the second comparator 204b. The voltage detection means 204 performs feedback control such that the first reference voltage Vs1 and the second reference voltage Vs2 are equal to the high-level voltage and the low-level voltage of the signal Sa input to the main amplifier 203, respectively, and gives the first and second reference voltages Vs1 and Vs2 as the high-level voltage and the low-level voltage to the center voltage calculation means 206.
As such, the NRZ signal amplifying device 201 performs feedback control such that the first reference voltage Vs1 is substantially equal to the low-level voltage of the signal S1 input to the main amplifier 203 and the second reference voltage Vs2 is substantially equal to the high-level voltage of the signal S1. That is, the first and second reference voltages Vs1 and Vs2 are given as the high-level voltage and the low-level voltage to the center voltage calculation means 206. Therefore, the center voltage Vcent of the NRZ signal S can be equal to the center voltage Vaa of the appropriate input range of the main amplifier 203.